Circuit Design: Efficient Power Amplification
Circuit Design: Efficient Power Amplification
Modern wireless communication waveforms exhibit high peak-to-average power ratios (PAPR). As a result, power amplifiers (PAs) spend most of their time operating at deep power back-off, where conventional linear-mode PAs are inherently inefficient. The Doherty PA has emerged as a promising architecture for back-off efficiency enhancement, particularly at mmWave frequencies, as it offers an “RF-in, RF-out” drop-in solution with minimal baseband computational overhead. However, most reported Doherty PAs are two-way symmetric Doherty, with back-off efficiency enhancements limited to only 6 dB, insufficient for efficient amplification of high-PAPR waveforms.
Our work spans multi-way Doherty PA architectures, Watt-level power combining, and compact transceiver front-end integration. We aim to extend efficiency enhancement beyond 6-dB back-off and achieve high output power, while maintaining a compact footprint comparable to traditional linear PAs.